HD64F2357VF13 Datasheet, PDF (559/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

15.3.6 Data Transfer Operations
Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary
when switching from transmit mode to receive mode, or vice versa.
[1] Clear the TE and RE bits in SCR to 0.
[2] Clear the error flags ERS, PER, and ORER in SSR to 0.
[3] Set the O/E bit and CKS1 and CKS0 bits in SMR. Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits
to 1.
[4] Set the SMIF, SDIR, and SINV bits in SCMR.
When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the
high-impedance state.
[5] Set the value corresponding to the bit rate in BRR.
[6] Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE and CKE1 bits to 0.
If the CKE0 bit is set to 1, the clock is output from the SCK pin.
[7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the
same time, except for self-diagnosis.
Serial Data Transmission: As data transmission in Smart Card mode involves error signal sampling and retransmission
processing, the processing procedure is different from that for the normal SCI. Figure 15-4 shows a flowchart for
transmitting, and figure 15-5 shows the relation between a transmit operation and the internal registers.
[1] Perform Smart Card interface mode initialization as described above in Initialization.
[2] Check that the ERS error flag in SSR is cleared to 0.
[3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1.
[4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is
cleared to 0.
[5] When transmitting data continuously, go back to step [2].
[6] To end transmission, clear the TE bit to 0.
With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible.
If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a
transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to
1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated.
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in
figure 15-6.
If the DMAC or DTC is activated by a TXI request, the number of bytes set in the DMAC or DTC can be transmitted
automatically, including automatic retransmission.
For details, see Interrupt Operations and Data Transfer Operation by DMAC or DTC below.
Rev.6.00 Oct.28.2004 page 529 of 1016
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