HD64F2357VF13 Datasheet, PDF (339/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port B Register (PORTB) (On-Chip ROM Version Only)
Bit
:
7
6
5
4
3
2
1
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Initial value : —*
—*
—*
—*
—*
—*
—*
—*
R/W
:
R
R
R
R
R
R
R
R
Note: * Determined by state of pins PB₇ to PB₀.
PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B
pins (PB₇ to PB₀) must always be performed on PBDR.
If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while
PBDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin states, as PBDDR and
PBDR are initialized. PORTB retains its prior state after a manual reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Port B MOS Pull-Up Control Register (PBPCR) (On-Chip ROM Version Only)
Bit
:
7
6
5
4
3
2
1
0
PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: Setting is prohibited in the H8S/2352, H8S/2394, H8S/2392, and H8S/2390.
PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an
individual bit basis.
When a PBDDR bit is cleared to 0 (input port setting) in mode 6 or 7, setting the corresponding PBPCR bit to 1 turns on
the MOS input pull-up for the corresponding pin.
PBPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual
reset*, and in software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Rev.6.00 Oct.28.2004 page 309 of 1016
REJ09B0138-0600H