HD64F2357VF13 Datasheet, PDF (273/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

8.1.3 Register Configuration
Table 8-1 summarizes the DTC registers.
Table 8-1 DTC Registers
Name
Abbreviation R/W Initial Value Address*¹
DTC mode register A
MRA
—*² Undefined
—*³
DTC mode register B
MRB
—*² Undefined
—*³
DTC source address register
SAR
—*² Undefined
—*³
DTC destination address register DAR
—*² Undefined
—*³
DTC transfer count register A
CRA
—*² Undefined
—*³
DTC transfer count register B
CRB
—*² Undefined
—*³
DTC enable registers
DTCER
R/W H'00
H'FF30 to H'FF35
DTC vector register
DTVECR
R/W H'00
H'FF37
Module stop control register
MSTPCR
R/W H'3FFF
H'FF3C
Notes: 1. Lower 16 bits of the address.
2. Registers within the DTC cannot be read or written to directly.
3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot be located in external
space. When the DTC is used, do not clear the RAME bit in SYSCR to 0.
Rev.6.00 Oct.28.2004 page 243 of 1016
REJ09B0138-0600H