HD64F2357VF13 Datasheet, PDF (565/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Normal operation
Software
standby
Normal operation
[1] [2] [3]
[4] [5] [6]
[7] [8] [9]
Figure 15-9 Clock Halt and Restart Procedure
Powering On: To secure the clock duty from power-on, the following switching procedure should be followed.
[1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential.
[2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
[3] Set SMR and SCMR, and switch to Smart Card mode operation.
[4] Set the CKE0 bit in SCR to 1 to start clock output.
15.4 Usage Notes
The following points should be noted when using the SCI as a Smart Card interface.
Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In Smart Card Interface mode,
the SCI operates on a basic clock with a frequency of 372 times the transfer rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
Receive data is latched internally at the rising edge of the 186th pulse of the basic clock. This is illustrated in figure 15-10.
372 clocks
186 clocks
0
185
371 0
Internal
basic
clock
Receive
data (RxD)
Start bit
D0
185
371 0
D1
Synchro-
nization
sampling
timing
Data
sampling
timing
Figure 15-10 Receive Data Sampling Timing in Smart Card Mode
Thus the reception margin in asynchronous mode is given by the following formula.
Rev.6.00 Oct.28.2004 page 535 of 1016
REJ09B0138-0600H