HD64F2357VF13 Datasheet, PDF (59/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to
section 5, Interrupt Controller.
Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts,
including NMI, are disabled for three states after one of these instructions is executed, except for STC.
(3) Condition-Code Register (CCR): This 8-bit register contains internal CPU status information, including an interrupt
mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit
setting.) The I bit is set to 1 by hardware at the start of an exception-handling sequence. For details, refer to section 5,
Interrupt Controller.
Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC,
and XORC instructions. With the H8S/2357 Group, this bit cannot be used as an interrupt mask bit.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed,
this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W,
or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise.
When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at
bit 27, and cleared to 0 otherwise.
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.
Bit 3—Negative Flag (N): Stores the value of the most significant bit (sign bit) of data.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to
Appendix A.1, Instruction List.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and
C flags are used as branching conditions for conditional branch (Bcc) instructions.
2.4.4 Initial Register Values
Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and
sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In
particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L
instruction executed immediately after a reset.
Rev.6.00 Oct.28.2004 page 29 of 1016
REJ09B0138-0600H