HD64F2357VF13 Datasheet, PDF (477/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12-9.
The control bits are set as follows:
[1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches
the constant in TCORA.
[2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at
a TCORB compare match.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with a pulse width
determined by TCORB. No software intervention is required.
H'FF
TCORA
TCORB
H'00
TCNT
Counter clear
TMO
Figure 12-9 Example of Pulse Output
Rev.6.00 Oct.28.2004 page 447 of 1016
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