HD64F2357VF13 Datasheet, PDF (579/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

16.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a on-chip sample-and-hold circuit. The A/D converter samples the analog input at a time t_D after
the ADST bit is set to 1, then starts conversion. Figure 16-5 shows the A/D conversion timing. Table 16-4 indicates the
A/D conversion time.
As indicated in figure 16-5, the A/D conversion time includes t_D and the input sampling time. The length of t_D varies
depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges
indicated in table 16-4.
In scan mode, the values given in table 16-4 apply to the first conversion time. In the second and subsequent conversions
the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1.
(1)
ø
Address bus ⁽²⁾
Write signal
Input sampling
timing
ADF
t_D
t_SPL
t _CONV
Legend:
(1):
ADCSR write cycle
(2):
ADCSR address
t_D:
t_SPL:
t_CONV:
A/D conversion start delay
Input sampling time
A/D conversion time
Figure 16-5 A/D Conversion Timing
Table 16-4 A/D Conversion Time (Single Mode)
Item
Symbol
A/D conversion start delay
t_D
Input sampling time
t _SPL
A/D conversion time
t _CONV
Note: Values in the table are the number of states.
CKS = 0
Min Typ Max Min
10 — 17 6
— 63 — —
259 — 266 131
CKS = 1
Typ Max
—9
31 —
— 134
Rev.6.00 Oct.28.2004 page 549 of 1016
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