HD64F2357VF13 Datasheet, PDF (146/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin.
Bit 0
WAITE
0
1
Description
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port.
Wait input by WAIT pin enabled
(Initial value)
6.2.6 Memory Control Register (MCR)
Bit
:
Initial value :
R/W
:
7
TPC
0
R/W
6
5
BE RCDM
0
0
R/W
R/W
4
CW2
0
R/W
3
MXC1
0
R/W
2
MXC0
0
R/W
1
RLW1
0
R/W
0
RLW0
0
R/W
MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number of precharge cycles,
access mode, address multiplexing shift size, and the number of wait states inserted during refreshing, when areas 2 to 5
are designated as DRAM interface.
MCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset* or in
software standby mode.
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (T_P) is to be used when areas 2 to 5
designated as DRAM space are accessed.
Bit 7
TPC
0
1
Description
1-state precharge cycle is inserted
2-state precharge cycle is inserted
(Initial value)
Bit 6—Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5 designated as DRAM
space. DRAM space burst access is performed in fast page mode.
Bit 6
BE
0
1
Description
Burst disabled (always full access)
For DRAM space access, access in fast page mode
(Initial value)
Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are designated as DRAM space and access to DRAM is
interrupted, RCDM selects whether the next DRAM access is waited for with the RAS signal held low (RAS down mode),
or the RAS signal is driven high again (RAS up mode).
Bit 5
RCDM
0
1
Description
DRAM interface: RAS up mode selected
DRAM interface: RAS down mode selected
(Initial value)
Rev.6.00 Oct.28.2004 page 116 of 1016
REJ09B0138-0600H