HD64F2357VF13 Datasheet, PDF (478/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

12.6 Usage Notes
Application programmers should note that the following kinds of contention can occur in the 8-bit timer.
12.6.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the clear takes priority, so that the
counter is cleared and the write is not performed.
Figure 12-10 shows this operation.
TCNT write cycle by CPU
T₁
T₂
ø
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 12-10 Contention between TCNT Write and Clear
Rev.6.00 Oct.28.2004 page 448 of 1016
REJ09B0138-0600H