HD64F2357VF13 Datasheet, PDF (132/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

If the same interrupt is selected as a DMAC activation source and a DTC activation source or CPU interrupt source,
operations are performed for them independently according to their respective operating statuses and bus mastership
priorities.
Table 5-11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the
DTA bit of DMABCR in the DMAC, the DTCE bit of DTCERA to DTCERF in the DTC and the DISEL bit of MRB in
the DTC.
Table 5-11 Interrupt Source Selection and Clearing Control
Settings
DMAC
DTC
Interrupt Source Selection/Clearing Control
DTA
DTCE
DISEL
DMAC
DTC
CPU
0
0
*
×
∆
1
0
∆
×
1
∆
1
*
*
∆
×
×
Legend:
∆ : The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
: The relevant interrupt is used. The interrupt source is not cleared.
× : The relevant bit cannot be used.
* : Don't care
5.6.4 Note on Use
SCI and A/D converter interrupt sources are cleared when the DMAC or DTC reads or writes to the prescribed register,
and are not dependent upon the DTA bit or DISEL bit.
Rev.6.00 Oct.28.2004 page 102 of 1016
REJ09B0138-0600H