HD64F2357VF13 Datasheet, PDF (564/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

and TEND flags are automatically cleared to 0 when data transfer is performed by the DMAC or DTC. In the event of an
error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the
DMAC is not activated. Thus, the number of bytes specified by the SCI and DMAC are transmitted automatically even in
retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and so the
RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag
will be cleared.
When performing transfer using the DMAC or DTC, it is essential to set and enable the DMAC or DTC before carrying
out SCI setting. For details of the DMAC and DTC setting procedures, see section 7, DMA Controller, and section 8, Data
Transfer Controller.
In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is
designated beforehand as a DMAC or DTC activation source, the DMAC or DTC will be activated by the RXI request,
and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is
performed by the DMAC or DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the
DMAC or DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should
be cleared.
15.3.7 Operation in GSM Mode
Switching the Mode: When switching between Smart Card interface mode and software standby mode, the following
switching procedure should be followed in order to maintain the clock duty.
• When changing from Smart Card interface mode to software standby mode
[1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed
output state in software standby mode.
[2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same
time, set the CKE1 bit to the value for the fixed output state in software standby mode.
[3] Write 0 to the CKE0 bit in SCR to halt the clock.
[4] Wait for one serial clock period.
During this interval, clock output is fixed at the specified level, with the duty preserved.
[5] Write H'00 to SMR and SCMR.
[6] Make the transition to the software standby state.
• When returning to Smart Card interface mode from software standby mode
[7] Exit the software standby state.
[8] Set the CKE1 bit in SCR to the value for the fixed output state (current SCK pin state) when software standby mode is
initiated.
[9] Set Smart Card interface mode and output the clock. Signal generation is started with the normal duty.
Rev.6.00 Oct.28.2004 page 534 of 1016
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