HD64F2357VF13 Datasheet, PDF (691/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 20 Clock Pulse Generator
20.1 Overview
The H8S/2357 Group has a on-chip clock pulse generator (CPG) that generates the system clock (ø), the bus master clock,
and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-speed clock divider, and a
bus master clock selection circuit.
20.1.1 Block Diagram
Figure 20-1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Oscillator
Duty
adjustment
circuit
SCKCR
SCK2 to SCK0
Medium-
speed
divider
ø/2 to ø/32 Bus master
clock
selection
circuit
System clock to ø pin
Internal clock
to supporting
modules
Bus master clock
to CPU, DTC,
and DMAC
Figure 20-1 Block Diagram of Clock Pulse Generator
20.1.2 Register Configuration
The clock pulse generator is controlled by SCKCR. Table 20-1 shows the register configuration.
Table 20-1 Clock Pulse Generator Register
Name
System clock control register
Note:* Lower 16 bits of the address.
Abbreviation R/W
SCKCR
R/W
Initial Value
H'00
Address*
H'FF3A
Rev.6.00 Oct.28.2004 page 661 of 1016
REJ09B0138-0600H