HD64F2357VF13 Datasheet, PDF (437/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Contention between TGR Read and Input Capture: If the input capture signal is generated in the T₁ state of a TGR
read cycle, the data that is read will be the data after input capture transfer.
Figure 10-53 shows the timing in this case.
ø
Address
Read signal
Input capture
signal
TGR
Internal
data bus
TGR read cycle
T₁
T₂
TGR address
X
M
M
Figure 10-53 Contention between TGR Read and Input Capture
Contention between TGR Write and Input Capture: If the input capture signal is generated in the T₂ state of a TGR
write cycle, the input capture operation takes precedence and the write to TGR is not performed.
Figure 10-54 shows the timing in this case.
ø
Address
Write signal
Input capture
signal
TCNT
TGR
TGR write cycle
T₁
T₂
TGR address
M
M
Figure 10-54 Contention between TGR Write and Input Capture
Rev.6.00 Oct.28.2004 page 407 of 1016
REJ09B0138-0600H