HD64F2357VF13 Datasheet, PDF (208/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit 12—Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for transfer in dual address mode
or single address mode.
Bit 12
SAE0
0
1
Description
Transfer in dual address mode
Transfer in single address mode
(Initial value)
This bit is invalid in full address mode.
Bits 11 to 8—Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is
performed, of the internal interrupt source selected by the data transfer factor setting.
When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared
automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer
factor setting does not issue an interrupt request to the CPU or DTC.
When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a
transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source
should be cleared by the CPU or DTC transfer.
When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the
CPU or DTC regardless of the DTA bit setting.
Bit 11—Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA transfer is performed, of
the internal interrupt source selected by the channel 1B data transfer factor setting.
Bit 11
DTA1B
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 10—Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA transfer is performed, of
the internal interrupt source selected by the channel 1A data transfer factor setting.
Bit 10
DTA1A
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Bit 9—Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA transfer is performed, of the
internal interrupt source selected by the channel 0B data transfer factor setting.
Bit 9
DTA0B
0
1
Description
Clearing of selected internal interrupt source at time of DMA transfer is disabled
(Initial value)
Clearing of selected internal interrupt source at time of DMA transfer is enabled
Rev.6.00 Oct.28.2004 page 178 of 1016
REJ09B0138-0600H