HD64F2357VF13 Datasheet, PDF (385/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit 7 Bit 6 Bit 5 Bit 4
Channel IOD3 IOD2 IOD1 IOD0 Description
3
0 0 0 0 TGR3D is Output disabled
(Initial value)
1
output _{Initial output is 0 0 output at compare match}
1
0
compare _output
register*²
1 output at compare match
1
Toggle output at compare
match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1 0 0 0 TGR3D is Capture input Input capture at rising edge
1
input
source is
capture TIOCD3 pin
1
×
register*²
Input capture at falling edge
Input capture at both edges
1
×
×
Capture input Input capture at TCNT4
source is channel count-up/count-down*¹
4/count clock
×: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4 count clock, this setting is
invalid and input capture is not generated.
2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input
capture/output compare is not generated.
Rev.6.00 Oct.28.2004 page 355 of 1016
REJ09B0138-0600H