HD64F2357VF13 Datasheet, PDF (269/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

(b) Write Data Buffer Function and DMAC Operation Timing
The DMAC can start its next operation during external access using the write data buffer function. Consequently, the
DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function
is disabled. Also, internal bus cycles maybe hidden, and not visible.
(c) Write Data Buffer Function and TEND Output
A low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an
internal bus cycle, and an external write cycle is executed in parallel with this cycle. Note, for example, that a low level
may not be output from the TEND pin if the write data buffer function is used when data transfer is performed between an
internal I/O register and on-chip memory.
If at least one of the DMAC transfer addresses is an external address, a low level is output from the TEND pin.
Figure 7-42 shows an example in which a low level is not output at the TEND pin.
ø
Internal address
DMA
read
DMA
write
Internal read signal
Internal write signal
External address
HWR, LWR
TEND
Not output
External write by CPU, etc.
Figure 7-42 Example in Which Low Level is Not Output at TEND Pin
Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in synchronization with
DMAC internal operations. The operation is as follows:
[1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2].
[2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3].
[3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and switches to [1].
After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed
by detection of a low level.
Activation Source Acceptance: At the start of activation source acceptance, a low level is detected in both DREQ pin
falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected.
Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before execution of the
DMABCRL write to enable transfer.
Rev.6.00 Oct.28.2004 page 239 of 1016
REJ09B0138-0600H