HD64F2357VF13 Datasheet, PDF (377/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is
counted using both edges, the input clock period is halved (e.g. ø/4 both edges = ø/2 rising edge). If phase counting mode
is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.
Bit 4
CKEG1
Bit 3
CKEG0
Description
0
0
Count at rising edge
(Initial value)
1
Count at falling edge
1
—
Count at both edges
Note: Internal clock edge selection is valid when the input clock is ø/4 or slower. This setting is ignored if the input clock is
ø/1, or when overflow/underflow of another channel is selected.
Bits 2 to 0—Time Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the TCNT counter clock. The clock source can
be selected independently for each channel. Table 10-4 shows the clock sources that can be set for each channel.
Table 10-4 TPU Clock Sources
Internal Clock
External Clock
Overflow/
Underflow
on Another
Channel ø/1 ø/4 ø/16 ø/64 ø/256 ø/1024 ø/4096 TCLKA TCLKB TCLKC TCLKD Channel
0
1
2
3
4
5
Legend:
: Setting
Blank: No setting
Channel
0
Bit 2
TPSC2
0
1
Bit 1
TPSC1
0
1
0
1
Bit 0
TPSC0
0
1
0
1
0
1
0
1
Description
Internal clock: counts on ø/1
(Initial value)
Internal clock: counts on ø/4
Internal clock: counts on ø/16
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
External clock: counts on TCLKD pin input
Rev.6.00 Oct.28.2004 page 347 of 1016
REJ09B0138-0600H