HD64F2357VF13 Datasheet, PDF (414/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD.
The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at
compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at
compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired
TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in
TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare
match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are
identical, the output value does not change when a compare match occurs.
In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation.
The correspondence between PWM output pins and registers is shown in table 10-7.
Table 10-7 PWM Output Registers and Output Pins
Output Pins
Channel
Registers
PWM Mode 1
PWM Mode 2
0
TGR0A
TIOCA0
TIOCA0
TGR0B
TIOCB0
TGR0C
TIOCC0
TIOCC0
TGR0D
TIOCD0
1
TGR1A
TIOCA1
TIOCA1
TGR1B
TIOCB1
2
TGR2A
TIOCA2
TIOCA2
TGR2B
TIOCB2
3
TGR3A
TIOCA3
TIOCA3
TGR3B
TIOCB3
TGR3C
TIOCC3
TIOCC3
TGR3D
TIOCD3
4
TGR4A
TIOCA4
TIOCA4
TGR4B
TIOCB4
5
TGR5A
TIOCA5
TIOCA5
TGR5B
TIOCB5
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
Rev.6.00 Oct.28.2004 page 384 of 1016
REJ09B0138-0600H