HD64F2357VF13 Datasheet, PDF (433/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC
or DMAC is activated, the flag is cleared automatically. Figure 10-46 shows the timing for status flag clearing by the
CPU, and figure 10-47 shows the timing for status flag clearing by the DTC or DMAC.
ø
Address
Write signal
Status flag
Interrupt
request
signal
TSR write cycle
T₁
T₂
TSR address
Figure 10-46 Timing for Status Flag Clearing by CPU
ø
Address
Status flag
Interrupt
request
signal
DTC/DMAC
read cycle
T₁
T₂
DTC/DMAC
write cycle
T₁
T₂
Source address
Destination
address
Figure 10-47 Timing for Status Flag Clearing by DTC/DMAC Activation
Rev.6.00 Oct.28.2004 page 403 of 1016
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