HD64F2357VF13 Datasheet, PDF (615/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit 0
PSU
0
1
Description
Program setup cleared
Program setup
[Setting condition]
When FWE = 1, and SWE = 1
(Initial value)
19.7.3 Erase Block Registers 1 and 2 (EBR1, EBR2)
Bit
7
6
5
4
3
EBR1
—
—
—
—
—
Initial value 0
0
0
0
0
Read/Write —
—
—
—
—
2
1
0
—
EB9 EB8
0
0
0
—
R/W R/W
Bit
7
6
5
4
3
2
1
0
EBR2
EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
Initial value 0
0
0
0
0
0
0
0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
EBR1 and EBR2 are registers that specify the flash memory erase area block by block; bits 1 and 2 in EBR1 and bits 7 to
0 in EBR2 are readable/writable bits. EBR1 and EBR2 are each initialized to H'00 by a reset, in hardware standby mode
and software standby mode, when a low level is input to the FWE pin, and when a high level is input to the FWE pin and
the SWE bit in FLMCR1 is not set. When a bit in EBR1 or EBR2 is set, the corresponding block can be erased. Other
blocks are erase-protected. Set only one bit in EBR1 or EBR2 (more than one bit cannot be set). When on-chip flash
memory is disabled, a read will return H'00, and writes are invalid.
The flash memory block configuration is shown in table 19-12.
Table 19-12 Flash Memory Erase Blocks
Block (Size)
EB0 (1 kbyte)
EB1 (1 kbyte)
EB2 (1 kbyte)
EB3 (1 kbyte)
EB4 (28 kbytes)
EB5 (16 kbytes)
EB6 (8 kbytes)
EB7 (8 kbytes)
EB8 (32 kbytes)
EB9 (32 kbytes)
Address
H'000000 to H'0003FF
H'000400 to H'0007FF
H'000800 to H'000BFF
H'000C00 to H'000FFF
H'001000 to H'007FFF
H'008000 to H'00BFFF
H'00C000 to H'00DFFF
H'00E000 to H'00FFFF
H'010000 to H'017FFF
H'018000 to H'01FFFF
Rev.6.00 Oct.28.2004 page 585 of 1016
REJ09B0138-0600H