HD64F2357VF13 Datasheet, PDF (192/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

6.11 Bus Arbitration
6.11.1 Overview
The H8S/2357 Group has a bus arbiter that arbitrates bus master operations.
There are three bus masters, the CPU, DTC, and DMAC, which perform read/write operations when they have possession
of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the
prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then
takes possession of the bus and begins its operation.
6.11.2 Operation
The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge
signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request
acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge
signal, it takes possession of the bus until that signal is canceled.
The order of priority of the bus masters is as follows:
(High) DMAC > DTC > CPU (Low)
An internal bus access by an internal bus master, external bus release, and refreshing, can be executed in parallel.
In the event of simultaneous external bus release request, refresh request, and internal bus master external access request
generation, the order of priority is as follows:
(High) Refresh > External bus release (Low)
(High) External bus release > Internal bus master external access (Low)
As a refresh and an external access by an internal bus master can be executed simultaneously, there is no relative order of
priority for these two operations.
Rev.6.00 Oct.28.2004 page 162 of 1016
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