HD64F2357VF13 Datasheet, PDF (101/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Section 4 Exception Handling
4.1 Overview
4.1.1 Exception Handling Types and Priority
As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is
prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in
order of priority. Trap instruction exceptions are accepted at all times, in the program execution state.
Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control
mode set by the INTM0 and INTM1 bits of SYSCR.
Table 4-1 Exception Types and Priority
Priority Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU enters
the power-on reset state when the NMI pin is high, or the
manual reset*⁴ state when the NMI pin is low.
Trace*¹
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit is set to 1
Interrupt
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued*²
Low
Trap instruction (TRAPA)*³ Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution
of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on
completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in program execution state.
4. Manual reset is only supported in the H8S/2357 ZTAT.
Rev.6.00 Oct.28.2004 page 71 of 1016
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