HD64F2357VF13 Datasheet, PDF (262/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is
issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing
a request according to the priority order shown in table 7-13.
During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the
end of the transfer.
Figure 7-35 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1.
DMA read DMA write
DMA read DMA write
DMA
DMA read DMA write read
ø
Address bus
RD
HWR
LWR
DMA control Idle Read Write
Idle Read Write
Idle Read Write
Read
Channel 0A Request clear
Channel 0B
Channel 1
Bus
release
Request Selection Request clear
hold
Request
hold
Non-
selection
Request _Selection ^{Request clear}
hold
Channel 0A
transfer
Bus
release
Channel 0B
transfer
Bus
release
Channel 1 transfer
Figure 7-35 Example of Multi-Channel Transfer
7.5.14 Relation between External Bus Requests, Refresh Cycles, the DTC, and the DMAC
There can be no break between a DMA cycle read and a DMA cycle write. This means that a refresh cycle, external bus
release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle.
In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh or external bus released
state may be inserted after a write cycle. Since the DTC has a lower priority than the DMAC, the DTC does not operate
until the DMAC releases the bus.
When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these DMA cycles can be
executed at the same time as refresh cycles or external bus release. However, simultaneous operation may not be possible
when a write buffer is used.
Rev.6.00 Oct.28.2004 page 232 of 1016
REJ09B0138-0600H