HD64F2357VF13 Datasheet, PDF (700/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit 3—Output Port Enable (OPE): Specifies whether the output of the address bus and bus control signals (CS0 to CS7,
AS, RD, HWR, LWR, CAS) is retained or set to the high-impedance state in software standby mode.
Bit 3
OPE
0
1
Description
In software standby mode, address bus and bus control signals are high-impedance
In software standby mode, address bus and bus control signals retain output state
(Initial value)
Bits 2 and 1—Reserved: These bits cannot be modified and are always read as 0.
Bit 0—Reserved: This bit can be read or written to, but only 0 should be written.
21.2.2 System Clock Control Register (SCKCR)
Bit
:
7
6
5
4
3
PSTOP —
—
—
—
Initial value :
0
0
0
0
0
R/W
: R/W
R/W —/(R/W)* —
—
Note: * R/W in the H8S/2390, H8S/2392, H8S/2394, and H8S/2398.
2
SCK2
0
R/W
1
SCK1
0
R/W
0
SCK0
0
R/W
SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.
Bit 7
PSTOP
0
1
Normal
Operating Mode
ø output (initial value)
Fixed high
Description
Sleep Mode
Software
Standby Mode
ø output
Fixed high
Fixed high
Fixed high
Hardware
Standby Mode
High impedance
High impedance
Bits 6—Reserved: This bit can be read or written to, but only 0 should be written.
Bit 5—Reserved: In the H8S/2357 and H8S/2352, this bit cannot be modified and is always read as 0. Only 0 should be
written. This bit is reserved in the H8S/2390, H8S/2392, H8S/2394 and H8S/2398. Only 0 should be written to this bit.
Bits 4 and 3—Reserved: These bits are always read as 0. Only 0 should be written to these bits.
Rev.6.00 Oct.28.2004 page 670 of 1016
REJ09B0138-0600H