HD64F2357VF13 Datasheet, PDF (851/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the
above instruction with an 8-bit bus, using three-state access with no wait states.
ø
Address bus
RD
HWR, LWR
High level
R:W 2nd
Fetching
3rd byte
of instruction
Fetching
4th byte
of instruction
Internal
operation
R:W EA
Fetching
1nd byte of
instruction at
jump address
Fetching
2nd byte of
instruction at
jump address
Figure A-1 Address Bus, RD, HWR, and LWR Timing
(8-Bit Bus, Three-State Access, No Wait States)
Rev.6.00 Oct.28.2004 page 821 of 1016
REJ09B0138-0600H