HD64F2357VF13 Datasheet, PDF (490/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

13.3 Operation
13.3.1 Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by
rewriting the TCNT value (normally be writing H'00) before overflows occurs. This ensures that TCNT does not overflow
while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other
error, the WDTOVF signal*¹ is output. This is shown in figure 13-4. This WDTOVF signal*¹ can be used to reset the
system. The WDTOVF signal*¹ is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2357 Group internally is
generated at the same time as the WDTOVF signal*¹. This reset can be selected as a power-on reset or a manual reset*²,
depending on the setting of the RSTS bit in RSTCSR. The internal reset signal is output for 518 states.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES
pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.
Notes: 1. In the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392, or H8S/2390, the WDTOVF pin function is not
available.
2. Manual reset is only supported in the H8S/2357 ZTAT.
TCNT count
H'FF
Overflow
H'00
WT/IT=1
TME=1
H'00 written
to TCNT
WDTOVF signal*³
WOVF=1
WDTOVF*³ and
internal reset are
generated
Time
WT/IT=1 H'00 written
TME=1 to TCNT
Internal reset signal*¹
132 states*²
Legend:
WT/IT: Timer mode select bit
TME: Timer enable bit
518 states
Notes: 1.
2.
3.
The internal reset signal is generated only if the RSTE bit is set to 1.
130 states when the RSTE bit is cleared to 0.
The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394,
H8S/2392, or H8S/2390.
Figure 13-4 Watchdog Timer Operation
Rev.6.00 Oct.28.2004 page 460 of 1016
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