HD64F2357VF13 Datasheet, PDF (210/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A.
Bit 4
DTE0A
0
1
Description
Data transfer disabled
Data transfer enabled
(Initial value)
Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC
when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer,
and issues a transfer end interrupt request to the CPU or DTC.
A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by
performing processing to continue transfer by setting the transfer counter and address register again, and then setting the
DTE bit to 1.
Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B transfer end interrupt.
Bit 3
DTIE1B
0
1
Description
Transfer end interrupt disabled
Transfer end interrupt enabled
(Initial value)
Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A transfer end interrupt.
Bit 2
DTIE1A
0
1
Description
Transfer end interrupt disabled
Transfer end interrupt enabled
(Initial value)
Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B transfer end interrupt.
Bit 1
DTIE0B
0
1
Description
Transfer end interrupt disabled
Transfer end interrupt enabled
(Initial value)
Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A transfer end interrupt.
Bit 0
DTIE0A
0
1
Description
Transfer end interrupt disabled
Transfer end interrupt enabled
(Initial value)
Rev.6.00 Oct.28.2004 page 180 of 1016
REJ09B0138-0600H