HD64F2357VF13 Datasheet, PDF (220/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

7.4 Register Descriptions (3)
7.4.1 DMA Write Enable Register (DMAWER)
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a
DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the
specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other
than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC.
Figure 7-2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt, and reactivating
channel 0A. The address register and count register area is re-set by the first DTC transfer, then the control register area is
re-set by the second DTC chain transfer.
When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the
contents of the other channels.
DTC
First transfer area
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
Second transfer area
using chain transfer
IOAR1B
ETCR1B
DMAWER
DMATCR
DMACR0A DMACR0B
DMACR1A DMACR1B
DMABCR
Bit
:
DMAWER :
Initial value :
R/W
:
Figure 7-2 Areas for Register Re-Setting by DTC (Example: Channel 0A)
7
6
5
4
3
2
1
0
—
—
—
—
WE1B WE1A WE0B WE0A
0
0
0
0
0
0
0
0
—
—
—
—
R/W
R/W
R/W
R/W
DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the DMACR, DMABCR,
and DMATCR by the DTC.
DMAWER is initialized to H'00 by a reset, and in standby mode.
Rev.6.00 Oct.28.2004 page 190 of 1016
REJ09B0138-0600H