HD64F2357VF13 Datasheet, PDF (436/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Contention between TGR Write and Compare Match: If a compare match occurs in the T₂ state of a TGR write cycle,
the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the
same value as before is written.
Figure 10-51 shows the timing in this case.
ø
Address
Write signal
Compare
match signal
TCNT
TGR
TGR write cycle
T₁
T₂
TGR address
N
N
TGR write data
Prohibited
N+1
M
Figure 10-51 Contention between TGR Write and Compare Match
Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T₂ state of a TGR
write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write.
Figure 10-52 shows the timing in this case.
ø
Address
Write signal
Compare
match signal
Buffer
register
TGR
TGR write cycle
T₁
T₂
Buffer register
address
Buffer register write data
N
M
N
Figure 10-52 Contention between Buffer Register Write and Compare Match
Rev.6.00 Oct.28.2004 page 406 of 1016
REJ09B0138-0600H