HD64F2357VF13 Datasheet, PDF (182/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Full access
T₁
T₂
Burst access
T₁
T₁
ø
Address bus
Only lower address changed
CS0
AS
RD
Data bus
Read data Read data Read data
Figure 6-30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)
6.7.3 Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the
initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control.
Wait states cannot be inserted in a burst cycle.
Rev.6.00 Oct.28.2004 page 152 of 1016
REJ09B0138-0600H