HD64F2357VF13 Datasheet, PDF (102/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4.1.2 Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:
1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack.
2. The interrupt mask bits are updated. The T bit is cleared to 0.
3. A vector address corresponding to the exception source is generated, and program execution starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
4.1.3 Exception Vector Table
The exception sources are classified as shown in figure 4-1. Different vector addresses are assigned to different exception
sources.
Table 4-2 lists the exception sources and their vector addresses.
Exception
sources
Reset
Trace
Interrupts
Power-on reset
Manual reset*
External interrupts: NMI, IRQ7 to IRQ0
Internal interrupts: 52 interrupt sources in
on-chip supporting modules
Trap instruction
Note: * Manual reset is only supported in the H8S/2357 ZTAT.
Figure 4-1 Exception Sources
In modes 6 and 7 the on-chip ROM available for use after a power-on reset is the 64-kbyte area comprising addresses
H'000000 to H'00FFFF. Care is required when setting vector addresses. In this case, clearing the EAE bit in BCRL enables
the 128-kbyte (256-kbyte)* area comprising address H'000000 to H'01FFFF (H'03FFFF)* to be used.
Note: * Since these values are different according to the on-chip ROM capacitance, see section 3.5, Memory Map in Each
Operating Mode.
Rev.6.00 Oct.28.2004 page 72 of 1016
REJ09B0138-0600H