HD64F2357VF13 Datasheet, PDF (129/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

5.5 Usage Notes
5.5.1 Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the
instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is
generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction,
and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there
is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-
priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared.
Figure 5-8 shows an example in which the TGIEA bit in the TPU’s TIER0 register is cleared to 0.
TIER0 write cycle by CPU
TGI0A exception handling
ø
Internal
address bus
Internal
write signal
TIER0 address
TGIEA
TGFA
TGI0A
interrupt signal
Figure 5-8 Contention between Interrupt Generation and Disabling
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
5.5.2 Instructions that Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all
interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these
instructions, the new value becomes valid two states after execution of the instruction ends.
Rev.6.00 Oct.28.2004 page 99 of 1016
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