HD64F2357VF13 Datasheet, PDF (12/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Item
19.18.2 Program-Verify Mode
Figure 19-48 Program/Program-
Verify Flowchart
22.3.6 Flash Memory
Characteristics
Table 22-21 Flash Memory
Characteristics (HD64F2398F20,
HD64F2398TE20)
Table 22-22 Flash Memory
Characteristics (HD64F2398F20T,
HD64F2398TE20T)
Page
639
724
Revision (See Manual for Details)
Figure 19-48 amended, note *6 added
Write pulse application subroutine
Sub-routine write pulse
Enable WDT
Set PSU bit in FLMCR1
Wait (y) µs
*6
Set P bit in FLMCR1
Wait (z1) µs or (z2) µs or (z3) µs *5*6
Clear P bit in FLMCR1
Wait (α) µs
*6
Clear PSU bit in FLMCR1
Wait (β) µs
*6
Disable WDT
End sub
Note: 7 Write Pulse Width
Number of Writes (n)
1
2
3
4
5
6
7
8
9
10
11
12
1...3
998
999
1000
Write Time (z) µs
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z...2
z2
z2
z2
Note: Use a (z3) µs write pulse for additional
programming.
RAM
Program data area
(128 bytes)
Reprogram data area
(128 bytes)
Additional program data
area (128 bytes)
Increment address
Start of programming
Start
Set SWE bit in FLMCR1
Wait (x) µs
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
*6
Store 128-byte program data in program
data area and reprogram data area
*4
n=1
m=0
Write 128-byte data in RAM reprogram _*1
data area consecutively to flash memory
Sub-routine-call
Write pulse
(z1) µs or (z2) µs
See note 7 regarding pulse width
switching.
*6
Set PV bit in FLMCR1
Wait (γ) µs
*6
H'FF dummy write to verify address
Wait (ε) µs
*6
Read verify data
*2
n←n+1
Read data = verify
NG
data?
OK
NG
6≥n?
OK
Additional program data computation
m=1
Transfer additional program data to
additional program data area
*4
Reprogram data computation
*3
Transfer reprogram data to reprogram _*4
data area
NG
128-byte
data verification
completed?
OK
Clear PV bit in FLMCR1
Wait (η) µs
*6
NG
6≥n?
OK
Sequentially write 128-byte data in
additional program data area in RAM to *1
flash memory
Write Pulse
(z3 µs additional write pulse)
*6
NG
m = 0?
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
*6
End of programming
NG
n ≥ N?
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
*6
Programming failure
Table 22-21 title amended
726
Table 22-22 added
Rev.6.00 Oct.28.2004 page vi of xxiv
REJ09B0138-0600H