HD64F2357VF13 Datasheet, PDF (905/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

DRAMCR—DRAM Control Register
H'FED7
Bus Controller
Bit
:
Initial value :
Read/Write :
7
RFSHE
0
R/W
6
RCW
0
R/W
5
RMODE
0
R/W
4
CMF
0
R/W
3
CMIE
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Refresh Counter Clock Select
0 0 0 Count operation disabled
1 Count uses ø/2
1 0 Count uses ø/8
1 Count uses ø/32
1 0 0 Count uses ø/128
1 Count uses ø/512
1 0 Count uses ø/2048
1 Count uses ø/4096
Compare Match Interrupt Enable
0 Interrupt request (CMI) by CMF flag disabled
1 Interrupt request (CMI) by CMF flag enabled
Compare Match Flag
0 [Clearing condition]
Cleared by reading the CMF flag when CMF = 1, then
writing 0 to the CMF flag
1 [Setting condition]
Set when RTCNT = RTCOR
Refresh Mode
0 DRAM interface: CAS-before-RAS refreshing used
1 Self-refreshing used
RAS-CAS Wait
0 Wait state insertion in CAS-before-RAS refreshing disabled
RAS falls in T_Rr cycle
1 One wait state inserted in CAS-before-RAS refreshing
RAS falls in T_Rc1 cycle
Refresh Control
0 Refresh control is not performed
1 Refresh control is performed
RTCNT—Refresh Timer Counter
Bit
:
7
6
H'FED8
5
4
Bus Controller
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
Read/Write :
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Internal clock count value
Rev.6.00 Oct.28.2004 page 875 of 1016
REJ09B0138-0600H