HD64F2357VF13 Datasheet, PDF (903/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

BCRL—Bus Control Register L
H'FED5
Bus Controller
Bit
:
Initial value :
Read/Write :
7
BRLE
0
R/W
6
BREQOE
0
R/W
5
EAE
1
R/W
4
LCASS
1
R/W
3
DDS
1
R/W
2
1
0
— WDBE WAITE
1
0
0
R/W
R/W
R/W
WAIT Pin Enable
0 Wait input by WAIT pin disabled
1 _{Wait input by WAIT pin enabled}
Write Data Buffer Enable
0 Write data buffer function not used
1 Write data buffer function used
Reserved
Only 1 should be written to this bit
DACK Timing Select
When DMAC single address transfer is performed in
0 DRAM/PSRAM space, full access is always executed
DACK signal goes low from Tr or T1 cycle
Burst access is possible when DMAC single address
1 transfer is performed in DRAM/PSRAM space
DACK signal goes low from Tc1 or T2 cycle
LCAS Select
Write 0 to this bit when using the DRAM interface
External Addresses H'010000 to H'01FFFF^*1 Enable
0 On-chip ROM
1 External addresses (in external expansion mode)
or reserved area^*2 (in single-chip mode)
Notes: 1. External addresses H'010000 to H'01FFFF for the H8S/2357
External addresses H'010000 to H'03FFFF for the H8S/2398
2. Do not access a reserved area.
BREQO Pin Enable
0 BREQO output disabled
1 BREQO output enabled
Bus Release Enable
0 External bus release is disabled
1 External bus release is enabled
Rev.6.00 Oct.28.2004 page 873 of 1016
REJ09B0138-0600H