HD64F2357VF13 Datasheet, PDF (546/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Where M : Reception margin (%)
N : Ratio of bit rate to clock (N = 16)
D : Clock duty (D = 0 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below.
When D = 0.5 and F = 0,
M = (0.5 –
1 _{) × 100%}
2 × 16
= 46.875%
... Formula (2)
However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
Restrictions on Use of DMAC or DTC
• When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 ø clock
cycles after TDR is updated by the DMAC or DTC. Misoperation may occur if the transmit clock is input within 4 ø
clocks after TDR is updated. (Figure 14-22)
• When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant SCI reception data full
interrupt (RXI).
SCK
TDRE
Serial data
t
LSB
D0
D1
D2
D3
D4
D5
D6
D7
Note: When operating on an external clock, set t >4 clocks.
Figure 14-22 Example of Clocked Synchronous Transmission by DTC
Operation before mode transition (for the H8S/2398, H8S/2394, H8S/2392, and H8S/2390)
Before a mode transition to module stop mode or software standby mode, SCR should be initialized first, then SMR, BRR,
and SCMR should be initialized.
Rev.6.00 Oct.28.2004 page 516 of 1016
REJ09B0138-0600H