HD64F2357VF13 Datasheet, PDF (107/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

4.4 Interrupts
Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 52 internal sources in
the on-chip supporting modules. Figure 4-3 classifies the interrupt sources and the number of interrupts of each type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), refresh timer, 16-bit
timer-pulse unit (TPU), 8-bit timer, serial communication interface (SCI), data transfer controller (DTC), DMA controller
(DMAC), and A/D converter. Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two
interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed
interrupt control.
For details of interrupts, see section 5, Interrupt Controller.
External
interrupts
NMI (1)
IRQ7 to IRQ0 (8)
Interrupts
Internal
interrupts
WDT*¹ (1)
Refresh timer*² (1)
TPU (26)
8-bit timer (6)
SCI (12)
DTC (1)
DMAC (4)
A/D converter (1)
Notes:
Numbers in parentheses are the numbers of interrupt sources.
1. When the watchdog timer is used as an interval timer, it generates
an interrupt request at each counter overflow.
2. When the refresh timer is used as an interval timer, it generates an
interrupt request at each compare match.
Figure 4-3 Interrupt Sources and Number of Interrupts
Rev.6.00 Oct.28.2004 page 77 of 1016
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