HD64F2357VF13 Datasheet, PDF (616/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

19.7.4 System Control Register 2 (SYSCR2)
Bit
7
6
5
4
3
2
1
0
—
—
—
— FLSHE —
—
—
Initial value 0
0
0
0
0
0
0
0
Read/Write —
—
—
—
R/W
—
—
—
SYSCR2 is an 8-bit readable/writable register that controls on-chip flash memory (in F-ZTAT versions).
SYSCR2 is initialized to H'00 by a reset and in hardware standby mode.
SYSCR2 is available only in the F-ZTAT version. In the masked ROM and ZTAT versions, this register cannot be
written to and will return an undefined value if read.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 0.
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers
(FLMCR1, FLMCR2, EBR1, and EBR2). Setting the FLSHE bit to 1 enables read/write access to the flash memory
control registers. If FLSHE is cleared to 0, the flash memory control registers are deselected. In this case, the flash
memory control register contents are retained.
Bit 3
FLSHE
0
1
Description
Flash control registers deselected in area H'FFFFC8 to H'FFFFCB
Flash control registers selected in area H'FFFFC8 to H'FFFFCB
(Initial value)
Bits 2 to 0—Reserved: These bits cannot be modified and are always read as 0.
19.7.5 RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory
programming. RAMER is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software
standby mode. RAMER settings should be made in user mode or user program mode.
Flash memory area divisions are shown in table 19-13. To ensure correct operation of the emulation function, the ROM
for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal
execution of an access immediately after register modification is not guaranteed.
Bit: 7
6
5
4
—
—
—
—
Initial value: 0
0
0
0
R/W: —
—
—
—
Bits 7 to 3—Reserved: These bits are always read as 0.
3
2
1
0
— RAMS RAM1 RAM0
0
0
0
0
—
R/W R/W R/W
Rev.6.00 Oct.28.2004 page 586 of 1016
REJ09B0138-0600H