HD64F2357VF13 Datasheet, PDF (83/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Bus cycle
T1
T2
ø
Address bus
AS
RD
HWR, LWR
Data bus
Unchanged
High
High
High
High-impedance state
Figure 2-17 Pin States during On-Chip Supporting Module Access
2.9.4 External Address Space Access Timing
The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In
three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller.
2.10 Usage Note
2.10.1 TAS Instruction
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not
generated by the Renesas H8S and H8/300 Series C/C++ compilers. If the TAS instruction is used as a user-defined
intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used.
Rev.6.00 Oct.28.2004 page 53 of 1016
REJ09B0138-0600H