HD64F2357VF13 Datasheet, PDF (58/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These
registers are functionally equivalent, providing a maximum sixteen 8-bit registers.
Figure 2-5 illustrates the usage of the general registers. The usage of each register can be selected independently.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Figure 2-5 Usage of General Registers
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used
implicitly in exception handling and subroutine calls. Figure 2-6 shows the stack.
SP (ER7)
Free area
Stack area
Figure 2-6 Stack
2.4.3 Control Registers
The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code
register (CCR).
(1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The
length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is
fetched, the least significant PC bit is regarded as 0.)
(2) Extended Control Register (EXR): This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to
I0).
Bit 7—Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this
bit is set to 1, a trace exception is generated each time an instruction is executed.
Bits 6 to 3—Reserved: These bits are reserved. They are always read as 1.
Rev.6.00 Oct.28.2004 page 28 of 1016
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