HD64F2357VF13 Datasheet, PDF (422/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Table 10-12 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
High level
Low level
High level
Low level
Legend:
: Rising edge
: Falling edge
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
Low level
High level
High level
Low level
Operation
Up-count
Don’t care
Down-count
Don’t care
Phase Counting Mode Application Example: Figure 10-33 shows an example in which phase counting mode is
designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to
detect the position or speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
Channel 0 operates with TCNT counter clearing by TGR0C compare match; TGR0A and TGR0C are used for the
compare match function, and are set with the speed control period and position control period. TGR0B is used for input
capture, with TGR0B and TGR0D operating in buffer mode. The channel 1 counter input clock is designated as the
TGR0B input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed.
TGR1A and TGR1B for channel 1 are designated for input capture, channel 0 TGR0A and TGR0C compare matches are
selected as the input capture source, and store the up/down-counter values for the control periods.
This procedure enables accurate position/speed detection to be achieved.
Rev.6.00 Oct.28.2004 page 392 of 1016
REJ09B0138-0600H