HD64F2357VF13 Datasheet, PDF (118/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

IRQnSCA, IRQnSCB
IRQnE
IRQn input
Edge/level
detection circuit
IRQnF
S
Q
R
IRQn interrupt
request
Clear signal
Note: n=7 to 0
Figure 5-2 Block Diagram of Interrupts IRQ7 to IRQ0
Figure 5-3 shows the timing of setting IRQnF.
ø
IRQn
input pin
IRQnF
Figure 5-3 Timing of Setting IRQnF
The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output.
However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as
an I/O pin for another function.
5.3.2 Internal Interrupts
There are 52 sources for internal interrupts from on-chip supporting modules.
• For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select
enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt
request is issued to the interrupt controller.
• The interrupt priority level can be set by means of IPR.
• The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request. When the DMAC or DTC is activated
by an interrupt, the interrupt control mode and interrupt mask bits are not affected.
5.3.3 Interrupt Exception Handling Vector Table
Table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the
lower the vector number, the higher the priority.
Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same
priority, and priorities within a module, are fixed as shown in table 5-4.
Rev.6.00 Oct.28.2004 page 88 of 1016
REJ09B0138-0600H