HD64F2357VF13 Datasheet, PDF (79/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Table 2-7 Exception Handling Types and Priority
Priority Type of Exception
Detection Timing
Start of Exception Handling
High
Reset
Synchronized with clock
Exception handling starts
immediately after a low-to-high
transition at the RES pin, or
when the watchdog timer
overflows.
Trace
End of instruction
execution or end of
exception-handling
sequence*¹
When the trace (T) bit is set to
1, the trace starts at the end of
the current instruction or current
exception-handling sequence
Interrupt
End of instruction
execution or end of
exception-handling
sequence*²
When an interrupt is requested,
exception handling starts at the
end of the current instruction or
current exception-handling
sequence
Trap instruction
Low
When TRAPA instruction Exception handling starts when
is executed
a trap (TRAPA) instruction is
executed*³
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the
RTE instruction.
2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after
reset exception handling.
3. Trap instruction exception handling is always accepted, in the program execution state.
(2) Reset Exception Handling
After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling
starts. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset* state when the NMI pin is
low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and
starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling
and after it ends.
Note : * Manual reset is only supported in the H8S/2357 ZTAT.
(3) Traces
Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace
mode is established, trace exception handling starts at the end of each instruction.
At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt
masks are not affected.
The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace
exception-handling routine, trace mode is entered again. Trace exception-handling is not executed at the end of the RTE
instruction.
Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit.
(4) Interrupt Exception Handling and Trap Instruction Exception Handling
When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the
program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in
the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution
starts from that start address.
Rev.6.00 Oct.28.2004 page 49 of 1016
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