HD64F2357VF13 Datasheet, PDF (592/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

18.2 Register Descriptions
18.2.1 System Control Register (SYSCR)
Bit
:
7
—
Initial value :
0
R/W
: R/W
6
5
4
3
2
— INTM1 INTM0 NMIEG —
0
0
0
0
0
—
R/W
R/W
R/W
—
1
0
—
RAME
0
1
R/W
R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section
3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is
released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
18.3 Operation
When the RAME bit is set to 1, accesses to addresses H'FFDC00 to H'FFFBFF* are directed to the on-chip RAM. When
the RAME bit is cleared to 0, the off-chip address space is accessed.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or
word units. Each type of access can be performed in one state.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address.
Note: * Since the on-chip RAM capacitance differs according to each product, see section 3.5, Memory Map in Each
Operating Mode.
18.4 Usage Note
DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is used, the RAME bit
must not be cleared to 0.
Rev.6.00 Oct.28.2004 page 562 of 1016
REJ09B0138-0600H