HD64F2357VF13 Datasheet, PDF (47/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

Type
Address bus
Symbol
A₂₃ to
A₀
Data bus
Bus control
D₁₅ to
D₀
CS7 to
CS0
AS
RD
HWR
LWR
CAS
WAIT
LCAS
DMA controller
(DMAC)
DREQ1,
DREQ0
TEND1,
TEND0
DACK1,
DACK0
Pin No.
TFP-120 FP-128B I/O Name and Function
28 to 25,
23 to 16,
14 to 7,
5 to 2
32 to 29,
27 to 20,
18 to 11,
9 to 6
Output Address bus: These pins output an
address.
51 to 48, 57 to 54, I/O
46 to 39, 52 to 45,
37 to 34 43 to 40
Data bus: These pins constitute a
bidirectional data bus.
120 to 117 128, 127,
61, 60, 69, 66,
30, 29 34, 33,
2, 1
Output
Chip select: Signals for selecting
areas 7 to 0.
82
90
Output Address strobe: When this pin is
low, it indicates that address output
on the address bus is enabled.
83
91
Output Read: When this pin is low, it
indicates that the external address
space can be read.
84
92
Output High write/write enable:
A strobe signal that writes to external
space and indicates that the upper
half (D₁₅ to D₈) of the data bus is
enabled.
The 2CAS type DRAM write enable
signal.
85
93
Output Low write:
A strobe signal that writes to external
space and indicates that the lower
half (D₇ to D₀) of the data bus is
enabled.
116
126
Output Upper column address
strobe/column address strobe:
The 2CAS type DRAM upper column
address strobe signal.
86
94
Input Wait: Requests insertion of a wait
state in the bus cycle when
accessing external 3-state address
space.
86
94
Output Lower column address strobe: The
2-CAS type DRAM lower column
address strobe signal
62, 60
70, 66
Input DMA request 1 and 0: These pins
request DMAC activation.
63, 61
71, 69
Output DMA transfer end 1 and 0: These
pins indicate the end of DMAC data
transfer.
112, 111 122, 121 Output DMA transfer acknowledge 1 and
0: These are the DMAC single
address transfer acknowledge pins.
Rev.6.00 Oct.28.2004 page 17 of 1016
REJ09B0138-0600H