HD64F2357VF13 Datasheet, PDF (434/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

10.7 Usage Notes
Note that the kinds of operation and contention described below occur during TPU operation.
Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and
at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the
pulse width must be at least 2.5 states. Figure 10-48 shows the input clock conditions in phase counting mode.
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Phase
Phase
differ-
differ-
Overlap ence Overlap ence
Pulse width
Pulse width
Pulse width
Pulse width
Notes: Phase difference and overlap: 1.5 states or more
Pulse width
: 2.5 states or more
Figure 10-48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual
counter frequency is given by the following formula:
f= ^ø
(N + 1)
Where
f : Counter frequency
ø : Operating frequency
N : TGR set value
Rev.6.00 Oct.28.2004 page 404 of 1016
REJ09B0138-0600H