HD64F2357VF13 Datasheet, PDF (112/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

5.1.2 Block Diagram
A block diagram of the interrupt controller is shown in Figure 5-1.
SYSCR
NMI input
IRQ input
INTM1, INTM0
NMIEG
NMI input unit
IRQ input unit
ISR
ISCR IER
Internal interrupt
request
SWDTEND to TEI
Interrupt controller
Priority
determination
IPR
CPU
Interrupt
request
Vector
number
I
I2 to I0
CCR
EXR
Legend:
ISCR: IRQ sense control register
IER: IRQ enable register
ISR: IRQ status register
IPR: Interrupt priority register
SYSCR: System control register
Figure 5-1 Block Diagram of Interrupt Controller
5.1.3 Pin Configuration
Table 5-1 summarizes the pins of the interrupt controller.
Table 5-1 Interrupt Controller Pins
Name
Symbol
Nonmaskable interrupt NMI
I/O
Input
External interrupt
requests 7 to 0
IRQ7 to IRQ0 Input
Function
Nonmaskable external interrupt; rising or
falling edge can be selected
Maskable external interrupts; rising, falling, or
both edges, or level sensing, can be selected
Rev.6.00 Oct.28.2004 page 82 of 1016
REJ09B0138-0600H