HD64F2357VF13 Datasheet, PDF (793/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

(5) Timing of On-Chip Supporting Modules
Table 22-40 lists the timing of on-chip supporting modules.
Table 22-40 Timing of On-Chip Supporting Modules
Condition B: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition C: V_CC = 3.0 V to 5.5 V, AV_CC = 3.0 V to 5.5 V, V_ref = 3.0 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 13 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
PORT
PPG
TPU
TMR
SCI
Condition B
Symbol Min Max
Output data delay time t _PWD
Input data setup time t _PRS
Input data hold time
t _PRH
Pulse output delay time t _POD
Timer output delay time t _TOCD
Timer input setup time t _TICS
Timer clock input setup t _TCKS
time
— 50
30 —
30 —
— 50
— 50
30 —
30 —
Timer clock Single t _TCKWH 1.5 —
pulse width edge
Both
t _TCKWL
2.5
—
edges
Timer output delay time t_TMOD
Timer reset input setup t_TMRS
time
— 50
30 —
Timer clock input setup t_TMCS
time
30 —
Timer clock Single t_TMCWH 1.5 —
pulse width edge
Both
t _TMCWL
2.5 —
edges
Input clock Asynchro- t _Scyc
4
—
cycle
nous
Synchro-
nous
6
—
Input clock pulse width
Input clock rise time
Input clock fall time
t _SCKW
t _SCKr
t _SCKf
0.4 0.6
— 1.5
— 1.5
Condition C
Min Max Unit
— 75
ns
50 —
50 —
— 75
ns
— 75
ns
50 —
50 —
ns
1.5 —
t _cyc
2.5 —
— 75
ns
50 —
ns
50 —
ns
1.5 —
t _cyc
2.5 —
4
—
t _cyc
6
—
0.4 0.6
t _Scyc
—
1.5
t _cyc
— 1.5
Test
Conditions
Figure 22-86
Figure 22-87
Figure 22-88
Figure 22-89
Figure 22-90
Figure 22-92
Figure 22-91
Figure 22-94
Rev.6.00 Oct.28.2004 page 763 of 1016
REJ09B0138-0600H