HD64F2357VF13 Datasheet, PDF (163/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

16-Bit 3-State Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. When a 16-bit
access space is accessed , the upper half (D₁₅ to D₈) of the data bus is used for the even address, and the lower half (D₇ to
D₀) for the odd address.
Wait states can be inserted.
Bus cycle
T₁
T₂
T₃
ø
Address bus
CSn
AS
RD
Read D₁₅ to D₈
Valid
D₇ to D₀
HWR
Write
LWR
D₁₅ to D₈
D₇ to D₀
Note: n = 0 to 7
Invalid
High
Valid
High impedance
Figure 6-11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access)
Rev.6.00 Oct.28.2004 page 133 of 1016
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