HD64F2357VF13 Datasheet, PDF (293/1049 Pages) Renesas Technology Corp – Old Company Name in Catalogs and Other Documents

[4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception data full (RXI)
interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception,
the CPU should be enabled to accept receive error interrupts.
[5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is
generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is
incremented and CRA is decremented. The RDRF flag is automatically cleared to 0.
[6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to
0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up
processing.
(2) Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used
to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG’s NDR is
performed in the first half of the chain transfer, and normal mode transfer to the TPU’s TGR in the second half. This is
because clearing of the activation source and interrupt generation at the end of the specified number of transfers are
restricted to the second half of the chain transfer (transfer when CHNE = 0).
[1] Perform settings for transfer to the PPG’s NDR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed
destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz = 1). Set the source side
as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR,
the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.
[2] Perform settings for transfer to the TPU’s TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed
destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table
start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value.
[3] Locate the TPU transfer register information consecutively after the NDR transfer register information.
[4] Set the start address of the NDR transfer register information to the DTC vector address.
[5] Set the bit corresponding to TGIA in DTCER to 1.
[6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER.
[7] Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output
is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger.
[8] Set the CST bit in TSTR to 1, and start the TCNT count operation.
[9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next
output trigger period is transferred to TGRA. The activation source TGFA flag is cleared.
[10] When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1,
the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be
performed in the interrupt handling routine.
(3) Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation.
The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector
address is H'04C0.
Rev.6.00 Oct.28.2004 page 263 of 1016
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